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5. Using HIL
Adding the HIL block to your Simulink model allows you to cosimulate a Quartus II
software design with a physical FPGA board implementing a portion of that design.
You define the contents and function of the FPGA by creating and compiling a
Quartus II project. A simple JTAG interface between Simulink and the FPGA board
links the two.
The main benefits of using the HIL block are faster simulation and richer
instrumentation. The Quartus II project you embed in an FPGA runs faster than a
software-only simulation. To further increase simulation speed, the HIL block offers
frame and burst modes of data transfer that are significantly faster than single-step
mode when you use it with suitable designs.
The HIL block also makes available to the hardware a large Simulink library of sinks
and sources, such as channel models and spectrum analyzers, which can give you
greater control and observability.
This chapter explains the HIL block design flow, walks through an example using the
HIL block, and discusses the optional burst and frame data transfer modes.
HIL Design Flow
The HIL block in AltLab library of the Altera DSP Builder Blockset enables the HIL
functionality. It represents the functions implemented on your FPGA, and works
smoothly with the normal DSP Builder/Simulink work flow.
The HIL design flow comprises the following steps:
1. Create a Quartus II project that defines the functions you want to co-simulate in
hardware and use Signal Compiler block to compile the Quartus II project
through the Quartus II Fitter.
2. Add the HIL block to your Simulink model and import the compiled Quartus II
project into the HIL block. You can also connect instrumentation to your HIL block
by adding additional blocks from the Simulink Sinks and Sources libraries.
1
If the original design contains a Clock block that defines a period and
sample time that is different from the default values, you must add a Clock
block with the same values as the HIL block.
3. Specify parameters for the HIL block, including the following options:
■
■
■
■
■
The Quartus II project to define its functionality
The clock and reset pins
The reset active level
The input and output pin characteristics
The use of single-step versus burst mode
4. Compile the HIL block to create a programming object file (. pof ) for hardware
cosimulation.
November 2013
Altera Corporation
DSP Builder Handbook
Volume 2: DSP Builder Standard Blockset
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